COD: alternative architectures for high speed packet switching

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Abstract
Current architectures for packet switches are ap- proaching the limit of electronic switching speed. This rakes the question of bow best to utilize reeent advances in photonic tech- nology in order to enable higher speed operation. In thii paper, we introduce cascoded opticol de&y line (COD) architectures for ultra high speed packet switching. The COD arehkctures utitiie an extremely simple distributed eleetmnic control algorithm to configure the states of 2 x 2 photosdc switches and use optical fiber delay lines to temporarily buffer paeketa if necessary. The simplicity of the arebiteetures may tdso make them suitable for "lightweight" atl-electronic implementations. For optical im- plementations, the number of 2 x 2 photonic switches used is a significant factor determining cost. We present a "baae~me" architecture for a '2 x 2 buffered packet switch that is work conserving (i.e. nonidting) and has the first-in, first-out (FIFO) property. If the arrival proeeases are independent and without memory, the maximum utilisation factor is (J, and the maximum acceptable packet 10ss probabllit y is c, then the required number of 2 x 2 photmdc switehea is ()(log(f)/ log (-~)), where ; = p?/ (p2 + -t - ~~1 ). If we modii the baseliie architecture by changing the delay line lengths then the system is no longer work conserving and loses the FIFO property, but the required number of 2 x 2 photonic switches is reduced to ()( log (log(F)/ log(T))). The required number of 2 x 2 photonic switches is essentiality insensitive to the distribution of packet arrivals, hut long delay tines are required for bursty traflic.

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