Abstract
In this paper, we present an `almost-all' optical packet switch architecture that does not rely on recirculating loops for storage implementation. Our architecture is based on two rearrangeably non-blocking stages interconnected by optical delay lines with different amount of delay. We've investigated the probability of loss as a function of link utilization and the size of the switch. In general, with proper setting of the number of delay lines, the switch can achieve arbitrarily low probability of loss. The latency characteristics of the switch were also investigated. Possible design of the electronic control circuit was shown. We estimated that transparent-bit-rate 32 X 32 switches may easily be implemented with ECL logic.© (1992) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.