Enhancement source-coupled logic for mixed-mode VLSI circuits
- 1 June 1992
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
- Vol. 39 (6) , 399-402
- https://doi.org/10.1109/82.145301
Abstract
Low-noise enhancement source-coupled logic (ESCL) is proposed for applications in high-precision mixed-mode integrated circuits (ICs). The differential ESCL topology offers potential low-power supply noise advantages over conventional CMOS logic for mixed-mode ICs by steering a constant current to perform the logic operation and it requires a smaller logic swing (ΔVL<0.2 Vdd) compared to static CMOS logic (ΔV=Vdd). For mixed-mode ICs, ESCL reduces the digital switching noise by approximately two orders of magnitude (`20-30 μA/gate) compared to conventional static logic spikes (0.5-1 mA/gate) which is essential to the development of sensitive on-chip analog circuitry. Results from several ESCL circuits implemented in a 2-μm p-well CMOS technology are presentedKeywords
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