A high performance CMOS process for submicron 16 Mb EPROM

7 January 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 591-594
https://doi.org/10.1109/iedm.1989.74350

Abstract

A high-performance and reliable 0.6 mu m CMOS process has been developed for the fabrication of next-generation 16-Mb density high-speed electrically programmable ROMs (EPROMs). The key process technologies are: (a) less than 0.2- mu m bird's beak isolation; (b) high-performance n/p channel LDD (lightly doped drain) transistors; (c) thin reliable interpoly dielectrics; (d) cold end processing using RTA (rapid thermal annealing) for both glass reflow and n/sup +/,p/sup +/ junction activation; and (e) less than 4.5- mu m/sup 2/ cell area (for practical die size) with fast writing speed, sufficient read current, and soft write endurance.<>

Keywords

This publication has 1 reference indexed in Scilit:

Device design for the submicrometer p-channel FET with n⁺polysilicon gate
IEEE Transactions on Electron Devices, 1984