Architecture and design of AlphaServer GS320
- 1 November 2000
- journal article
- Published by Association for Computing Machinery (ACM) in ACM SIGPLAN Notices
- Vol. 35 (11) , 13-24
- https://doi.org/10.1145/356989.356991
Abstract
This paper describes the architecture and implementation of the AlphaServer GS320, a cache-coherent non-uniform memory access multiprocessor developed at Compaq. The AlphaServer GS320 architecture is specifically targeted at medium-scale multiprocessing with 32 to 64 processors. Each node in the design consists of four Alpha 21264 processors, up to 32GB of coherent memory, and an aggressive IO subsystem. The current implementation supports up to 8 such nodes for a total of 32 processors. While snoopy-based designs have been stretched to medium-scale multiprocessors by some vendors, providing sufficient snoop bandwidth remains a major challenge especially in systems with aggressive processors. At the same time, directory protocols targeted at larger scale designs lead to a number of inherent inefficiencies relative to snoopy designs. A key goal of the AlphaServer GS320 architecture has been to achieve the best-of-both-worlds, partly by exploiting the bounded scale of the target systems.This paper focuses on the unique design features used in the AlphaServer GS320 to efficiently implement coherence and consistency. The guiding principle for our directory-based protocol is to address correctness issues related to rare protocol races without burdening the common transaction flows. Our protocol exhibits lower occupancy and lower message counts compared to previous designs, and provides more efficient handling of 3-hop transactions. Furthermore, our design naturally lends itself to elegant solutions for deadlock, livelock, starvation, and fairness. The AlphaServer GS320 architecture also incorporates a couple of innovative techniques that extend previous approaches for efficiently implementing memory consistency models. These techniques allow us to generate commit events (which are used for ordering purposes) well in advance of formulating the reply to a transaction. Furthermore, the separation of the commit event allows time-critical replies to bypass inbound requests without violating ordering properties. Even though our design specifically targets medium-scale servers, many of the same techniques can be applied to larger-scale directory-based and smaller-scale snoopy-based designs. Finally, we evaluate the performance impact of some of the above optimizations and present a few competitive benchmark results.Keywords
This publication has 20 references indexed in Scilit:
- The future of systems researchComputer, 1999
- The Alpha 21264 microprocessorIEEE Micro, 1999
- Starfire: extending the SMP envelopeIEEE Micro, 1998
- Towards transparent and efficient software distributed shared memoryPublished by Association for Computing Machinery (ACM) ,1997
- DiscoPublished by Association for Computing Machinery (ACM) ,1997
- Design and performance of the Shasta distributed shared memory protocolPublished by Association for Computing Machinery (ACM) ,1997
- A single-chip multiprocessorComputer, 1997
- The Scalable Coherent Interface (SCI)IEEE Communications Magazine, 1996
- Lazy cachingACM Transactions on Programming Languages and Systems, 1993
- A lazy cache algorithmPublished by Association for Computing Machinery (ACM) ,1989