An ultra low power lateral bipolar polysilicon emitter technology on SOI

30 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

No. 01631918,p. 75-78
https://doi.org/10.1109/iedm.1993.347395

Abstract

Until now the lateral bipolar transistor on SOI has been presented as an option in a CMOS process. In this investigation we show that this device structure is also very attractive for purely bipolar applications, enabling high frequency operation at ultra low power levels. Excellent devices with emitter areas down to 0.15 /spl mu/m/sup 2/, with scaled junction capacitances and f/sub T/ as high as 15 GHz are demonstrated. Due to the properly scaled junction capacitances a f/sub max/ of 15 GHz is realised at collector currents as low as 15 /spl mu/A.

Keywords

ETCHING
FREQUENCY
SILICON
FABRICATION
BIPOLAR TRANSISTORS
CAPACITANCE
CMOS TECHNOLOGY
RESISTS
ANISOTROPIC MAGNETORESISTANCE
LABORATORIES

This publication has 1 reference indexed in Scilit:

A high-performance lateral bipolar transistor fabricated on SIMOX
IEEE Electron Device Letters, 1993