Address calculation for retargetable compilation and exploration of instruction-set architectures
- 24 August 2005
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 597-600
- https://doi.org/10.1109/dac.1996.545645
Abstract
The advent of parallel executing address calculation units (ACUs) in digital signal processor (DSP) and application specific instruction-set processor (ASIP) architectures has made a strong impact on an application's ability to efficiently access memories. Unfortunately, successful compiler techniques which map high-level language data constructs to the addressing units of the architecture have lagged far behind. Since access to data is often the most demanding task in DSP, this mapping can be the most crucial function of the compiler. This paper introduces a new retargetable approach and prototype tool for the analysis of array references and traversals for efficient use of ACUs. The ArrSyn utility is designed to be used either as an enhancement to an existing dedicated compiler or as an aid for architecture exploration Author(s) Liem, C. TIMA Lab., Inst. Nat. Polytech. de Grenoble, France Paulin, P. ; Jerrava, A.Keywords
This publication has 7 references indexed in Scilit:
- Instruction-set matching and selection for DSP and ASIP code generationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- MPEG audio decoder for consumer applicationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Industrial experience using rule-driven retargetable code generation for multimedia applicationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Code Optimization Techniques for Embedded DSP MicroprocessorsProceedings of the 39th conference on Design automation - DAC '02, 1995
- Compiler transformations for high-performance computingACM Computing Surveys, 1994
- Loop ParallelizationPublished by Springer Nature ,1994
- Efficient program tracingComputer, 1993