A 4th-order Bandpass Sigma-delta Modulator
- 24 August 2005
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 16.5.1-16.5.4
- https://doi.org/10.1109/cicc.1992.591320
Abstract
This paper presents a Bandpass Σ∆ Modulator, which can be used in the new generation wireless communication receiver. It converts analog signals to the digital domain at the intermediate-frequency (IF). The modulator is implemented in the UMC 0.5µm CMOS 2p2m process. The power supply is ±2.5V. Bandwidth is 200kHz centered at 5Mhz. The sampling frequency of this circuit is 20MHz, which requires an op-amp gain of 61.5 dB to achieve a modulator SNR of 65dB.Keywords
This publication has 3 references indexed in Scilit:
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- One bit higher order sigma-delta A/D convertersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1990
- Bandpass sigma-delta modulationElectronics Letters, 1989