Implementation of IEEE single precision floating point addition and multiplication on FPGAs
- 1 January 1996
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 107-116
- https://doi.org/10.1109/fpga.1996.564761
Abstract
Floating point operations are hard to implement on FPGAs because of the complexity of their algorithms. On the other hand, many scientific problems require floating point arithmetic with high levels of accuracy in their calculations. Therefore, we have explored FPGA implementations of addition and multiplication for IEEE single precision floating-point numbers. Customizations were performed where this was possible in order to save chip area, or get the most out of our prototype board. The implementations tradeoff area and speed for accuracy. The adder is a bit-parallel adder, and the multiplier is a digit-serial multiplier. Prototypes have been implemented on Altera FLEX8000s, and peak rates of 7 MFlops for 32-bit addition and 2.3 MFlops for 32-bit multiplication have been obtained.Keywords
This publication has 2 references indexed in Scilit:
- Quantitative analysis of floating point arithmetic on FPGA based custom computing machinesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Digit-Serial ComputationPublished by Springer Nature ,1995