A Model for the Failure of Bipolar Silicon Integrated Circuits Subjected to Electrostatic Discharge

Abstract
The results are presented of a study into the mechanism by which failure occurs in an integrated circuit when it is subjected to a discharge of static electricity. The current that flows through an integrated circuit during a static discharge is shown to be an exponentially decaying current pulse. The peak value and rate of decay of the pulse can be calculated through the use of suitable equivalent circuits. Experimental data was obtained by using a simple test apparatus to simulate the current pulses caused by an electrostatic discharge. The power density and temperature rise at critical locations in the integrated circuit were calculated by using the current expression and the relevant physical and electrical properties of the I. C. Failure was found to occur when the temperature near a junction reached the approximate melting point of silicon. As a consequence of this study, a technique is derived which will permit the prediction of approximate threshold levels of static voltage that will produce failure under various conditions.