A graph theoretic technique for the generation of systolic implementations for shift-invariant flow graphs

24 March 2005

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. 9, 306-309
https://doi.org/10.1109/icassp.1984.1172406

Abstract

This paper presents a general method for the transformation of algorithms described by shift-invariant fully-specified flow graphs into equivalent systolic realizations. The method consists of a set of rules for the systematic manipulation of the flow graphs into systolic form utilizing a set of theorems from graph theory. It is shown that many of the previously published systolic algorithms and many new algorithms can be generated using this single procedure.

Keywords

FLOW GRAPHS
PIPELINES
DELAY EFFECTS
SAMPLING METHODS
ADDED DELAY
DISTRIBUTED COMPUTING
OPTIMAL CONTROL
CONTROL SYSTEMS
SYSTOLIC ARRAYS
INTERLEAVED CODES

This publication has 1 reference indexed in Scilit:

The maximum sampling rate of digital filters under hardware speed constraints
IEEE Transactions on Circuits and Systems, 1981