A CMOS adaptive line equalizer
- 1 October 1984
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 19 (5) , 788-793
- https://doi.org/10.1109/JSSC.1984.1052222
Abstract
A single-chip adaptive line equalizer for a digital transmission system has been developed using a high-frequency switched-capacitor filter technique. The equalizer, consisting of a /spl radic/f and decision-feedback bridged-tap equalizer, is fabricated in a CMOS technology with an effective channel length of 2 /spl mu/m. This permits the use of a 1.6-MHz sampled high-frequency switched-capacitor filter and makes it possible to achieve a small chip size of 6.0/spl times/4.2 mm. This LSI chip can automatically equalize line-loss of up to 42 dB and chemical bridged-tap echoes up to two time slots away from signal pulses at 200 kb/s burst frequency.Keywords
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