Considerations For Hardware Implementations Of Neural Networks
- 24 August 2005
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 2 (10586393) , 649-653
- https://doi.org/10.1109/acssc.1988.754628
Abstract
In constructing electronic hardware neural networks, algorithms as well as circuitry must be designed in a manner tolerant of limitations imposed by the implementation medi- um. Two development efforts are described in which hardware and algorithms are designed to operate within space, dynamic range, and noise constraints of analog CMOS VLSI technology. The performance of a single-layer feedback network incorporating simple binary interconnects is extended by using an analog prompt method. A "building block" approach for the design of multilayer feedforward networks is made possible by a new learning algorithm tolerant of hardware limitations.This publication has 5 references indexed in Scilit:
- Architecture for large microelectronic supervised learning artificial neural networks using a hybrid digital-analog approachNeural Networks, 1988
- A neural network for Euclidean distance minimizationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1988
- Electronic hardware implementations of neural networksApplied Optics, 1987
- Electronic Implementation of Associative Memory Based on Neural Network ModelsIEEE Transactions on Systems, Man, and Cybernetics, 1987
- Neural networks and physical systems with emergent collective computational abilities.Proceedings of the National Academy of Sciences, 1982