CMOS distributed amplifier design using CAD optimization techniques
- 20 January 2003
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A four-stage distributed amplifier exhibits 6.5 dB gain, 5.5 GHz bandwidth, and 80 mW power dissipation from a 3 V supply in 0.6 /spl mu/m CMOS. Scalable inductor models and custom CAD tools optimize performance.Keywords
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