Codes to reduce switching transients across VLSI I/O pins
- 1 September 1992
- journal article
- Published by Association for Computing Machinery (ACM) in ACM SIGARCH Computer Architecture News
- Vol. 20 (4) , 17-21
- https://doi.org/10.1145/142880.142888
Abstract
We develop a coding scheme that reduces switching transients by limiting the number of lines that simultaneously switch during transmission of address and data information over the I/O pins of a VLSI chip, or the lines of a system bus. The maximum number of lines that simultaneously switch can be reduced by a factor of two using simple and fast circuitry for encoding and decoding.Keywords
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