0.5-μm-pitch copper-dual-damascene metallization using organic SOG (k=2.9) for 0.18-μm CMOS applications

22 January 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 619-622
https://doi.org/10.1109/iedm.1999.824229

Abstract

We developed 0.5 /spl mu/m-pitch Cu-dual-damascene metallization by using very low-k organic SOG (HSG-R7; Hitachi Chemical Co., k=2.9) as the ILD. Interconnects using HSG reduced the interconnect capacitance by 30% compared to that of interconnects using TEOS. Furthermore, the electrical characteristics, such as line and via resistances, show that the HSG-ILD combination is feasible for 0.18-/spl mu/m CMOS applications.

Keywords

METALLIZATION
ETCHING
DELAY EFFECTS
PLASMA APPLICATIONS
PLASMA TEMPERATURE
TIN
CONDUCTIVE FILMS
LOGIC DEVICES
PLASMA PROPERTIES
PLASMA STABILITY

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