Modeling integrated injection logic (I/sup 2/L) performance and operational limits

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Abstract
A new user-oriented I/SUP 2/L macromodel is presented which models I/SUP 2/L performance and predicts operational limits. The macromodel includes n-p-n current gain falloff and injector transport efficiency falloff at both low and high operating currents. Lateral current transfer between adjacent gates may be included in the macromodel. A straightforward parameter measurement scheme is given which requires only simple test gates. The macromodel is easily implemented in commonly available circuit simulators such as SPICE. The modeling of I/SUP 2/L dynamic behavior is demonstrated with computer simulations of a five-stage ring oscillator and `D' flip-flop, where typically 15 percent or better agreement with measured data has been achieved. It is also shown that operational limits of I/SUP 2/L circuits can be accurately predicted. Computer simulation of I/SUP 2/L performance as a function of temperature is discussed. The macromodel is well suited for worst case analysis of I/SUP 2/L, and the close correspondence of the macromodel's parameters to gate geometry makes it possible to use the macromodel to approximately simulate performance changes with layout and geometry variations.

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