Spur reduction techniques in direct digital synthesizers
- 30 December 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
This paper reviews spur reduction techniques used in direct digital synthesizers (DDSs) or numerically controlled oscillators (NCOs). First, the classification and operation of conventional DDSs are reviewed. Covered are the pulse output DDS, sine output DDS, fractional divider, and phase interpolation DDS. It is shown that DDSs produce spurs as well as the desired output frequency due to the aliasing of harmonic imperfections in the generated waveform. Next, spur reduction techniques which reduce spurs by destroying the coherence of the aliasing process are discussed. Architectures described are the spurless fractional divider, the Wheatley jitter injection DDS, the randomized DAC DDS, and the nonuniform clock DDS. The spur reduction and phase jitter properties of each architecture are also discussed.Keywords
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