Modeling data flow and control flow for high level memory management
- 2 January 2003
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
The goal of this paper is to advocate a control flowindependent modeling of data flow in applicative algorithmspecifications. The model is utilized in the synthesisof ASIC architectures for real-time signal processingapplications. It allows for a generalization ofcontrol flow transformations which are used to optimizethe memory organization at an early stage in thesynthesis trajectory. Arguments supporting the inherentamenity of this type of model for use in efficaciousmemory...Keywords
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