A CMOS MONOLITHIC CHUA'S CIRCUIT

1 June 1993

journal article
Published by World Scientific Pub Co Pte Ltd in Journal of Circuits, Systems and Computers

Vol. 3 (2) , 259-268
https://doi.org/10.1142/s0218126693000198

Abstract

This paper presents the schematics and layout for a 2.4 µm CMOS prototype of the Chua's circuit. Our design uses VCCSs, realized using the quasilinear region of the transfer characteristics of a differential pair. The global, nonlinear characteristics of this building block are exploited to realize the Chua's diode. The prototype occupies 0.35 mm ² and consumes 1.6 mW for a symmetrical biasing of ±2.5 v . The HSPICE electrical simulation results of the extracted layout show bifurcation towards a double-scroll Chua's attractor by changing a bias current. The manufacturability of the prototype has been confirmed by Monte Carlo analysis. Measurements from the chip also show bifurcation towards the double-scroll.

Keywords

CMOS MONOLITHIC CHUA'S CIRCUIT

This publication has 0 references indexed in Scilit: