Wire-routing machines—New tools for VLSI physical design

1 January 1983

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in Proceedings of the IEEE

Vol. 71 (1) , 57-65
https://doi.org/10.1109/PROC.1983.12527

Abstract

Interconnection of components in a VLSI chip is becoming an increasingly complex problem. In this paper we examine the complexity of the wire routing process and discuss several new approaches to solving the problem using a parallel system architecture. The machines discussed range from compact systems for highly specialized applications to more general designs suited for broader applications. The process speedup due to parallelism and the cost advantage due to the use of large numbers of identical VLSI parts make these new machines practical today.

Keywords

VERY LARGE SCALE INTEGRATION
WIRE
WIRING
ROUTING
PROCESS DESIGN
INTEGRATED CIRCUIT INTERCONNECTIONS
LOGIC DESIGN
LOGIC TESTING
POLYNOMIALS
PROGRAMMABLE LOGIC ARRAYS

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