A 64 parallel integrated memory array processor and a 30 GIPS real-time vision system
- 19 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 242-249
- https://doi.org/10.1109/camp.1995.521046
Abstract
Describes a parallel-processor LSI chip (the Integrated Memory Array Processor, IMAP) and a compact real-time vision system (RVS-2). The IMAP integrates 64 8-bit processors, which operate in a SIMD manner, and 2-Mbit image memory on a single chip, and has peak performance of 3.84 GIPS. The RVS-2 consists of 8 IMAPs, a video interface, a control LSI chip (the Real-time Vision System Controller, RVSC) and a host workstation. RVSC is a 16-bit processor which carries out global data operations as well as providing an instruction stream to IMAP processors. In the RVS-2 system, the IMAP processors accomplish data-parallel operations, the RVSC applies global data operations to the results, and the host workstation carries out higher-level recognition tasks using the results obtained by the IMAPs and the RVSC. The peak performance of the RVS-2 is 30 GIPS and most of the basic image processing is carried out in 0.1 to 0.7 ms, which is 50 to 300 times faster the video rate.Keywords
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