Digital timing recovery circuit with feedback delay compensators for magnetic recording systems
- 1 January 1993
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Timing recovery circuits in magnetic recording systems have to have high bit rate and fast acquisition cycles, so they are usually equipped with an analog phase-locked loop (PLL). We propose a new method of digital timing recovery circuit that is different from the conventional digital PLL and that can be operated under a faster acquisition and wider capture range. This report describes the new digital timing recovery circuit architecture for magnetic recording that uses feedback delay compensators for fast acquisition and wide capture range on CMOS LSI circuit.Keywords
This publication has 2 references indexed in Scilit:
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- Response of an All Digital Phase-Locked LoopIEEE Transactions on Communications, 1974