Design tradeoffs in stall-control circuits for 600 MHz instruction queues
- 27 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A 600 MHz superscalar Alpha microprocessor contains separate integer and floating-point issue units. The integer issue unit selects up to four data-ready instructions to issue out of a 20-entry queue. The floating-point issue unit, similarly, selects two instructions out of a separate 15-entry queue. Though their operation is similar, the two queues required different tradeoffs to meet design goals. This paper first describes functions common to both queues, then discusses specific tradeoffs made in the implementation of each queue's stall control circuits.Keywords
This publication has 3 references indexed in Scilit:
- A 600 MHz superscalar RISC microprocessor with out-of-order executionPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- The Alpha 21264: a 500 MHz out-of-order execution microprocessorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Issue Logic For A 600 MHz Out-of-order ExecutionPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1997