High-swing, high-drive CMOS buffer
- 1 January 1995
- journal article
- Published by Institution of Engineering and Technology (IET) in IEE Proceedings - Circuits, Devices and Systems
- Vol. 142 (2) , 109-112
- https://doi.org/10.1049/ip-cds:19951683
Abstract
The advent of analogue and hybrid VLSI circuits has created new requirements for the design of many previously known building blocks. For example, implementation of cascaded multilayer analogue/hybrid neural networks requires output drivers that can charge the large number of interconnecting lines, and remain stable in the presence of large capacitive loads. A CMOS high dynamic range, high-drive buffer suitable for driving large capacitive loads is presented in this paper. An area-efficient output stage has been used, with which a rail-to-rail drive capability into a 5000 pF load at 160 kHz is achieved. The circuit occupies only 110 mils2 in a 3 µm technology. The output range is rail to rail for R>10 k Omega . The buffer is capable of driving resistive loads down to 300 Omega with acceptable THD.Keywords
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