Catastrophic source-drain burnout is an important failure mode in GaAs power FET's. In this paper we show that short-term (instantaneous) and long-term (aging) failures have different physical origins provided the underlying drain ohmic-contact weakness has been suppressed by use of a recessed n+drain ledge geometry. With this drain configuration, instantaneous burnout is due to thermal runaway of the buffer/substrate when local temperatures reach the 500-550°C range. For our typical devices With 30-50-µm-thick substrates, the associated de burnout power is 4-5 W/mm of gate periphery. Long-term aging failure, on the other hand, results from chemical changes at the GaAs surface between gate and drain. These changes induce localized areas of avalanche white-light emission, particularly along the n+ledge, which serve as burnout precursors. A series of aging, surface etching, and passivation experiments has revealed that oxygen probably plays a major role in the aging process, perhaps through its known effect on free arsenic formation. Moreover, it is found that minimization of the oxygen content at the top surface by using si3N4:H passivation rather than SiO2not only prevents white-light emission but increases the median life at 310°C channel temperature from 2.5 to more than 500 h.