A 300Mb/s clock recovery and data retiming system

23 March 2005

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 188-189
https://doi.org/10.1109/isscc.1987.1157134

Abstract

A single bipolar chip housed with a Surface Acoustic Wave filter in a multi-cavity ceramic DIP to provide clock recovery and data retiming up to 300Mb/s will be discussed. Device accepts a jittered data input and provides a low jitter clock ( rms)and retimed data with 10% eye width closure on ECL balanced outputs.

Keywords

CLOCKS
SAW FILTERS
DELAY
CAPACITANCE
RLC CIRCUITS
FREQUENCY
SURFACE ACOUSTIC WAVES
TEMPERATURE
VOLTAGE
PULSE AMPLIFIERS

This publication has 1 reference indexed in Scilit:

A regenerator chip set for high speed digital transmission
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1984