A submicrometer megabit DRAM process technology using trench capacitors

1 February 1985

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices

Vol. 32 (2) , 210-216
https://doi.org/10.1109/t-ed.1985.21931

Abstract

This paper describes guidelines for developing a 1-4-Mbit DRAM process, and device/process technologies for fabricating an experimental 1-Mbit DRAM. A single transistor cell combined with a trench capacitor and on-chip ECC technologies has the potential to realize a cell size of 10 µm ² without degrading soft error immunity. A depletion trench capacitor, submicrometer n-well CMOS process, Mo-poly gate, and submicrometer pattern formation technologies are developed, and an experimental 1-Mbit DRAM with a cell size of 20 µm ² is successfully developed by using these technologies.

Keywords

SUBMICROMETER
MBIT DRAM
TRENCH CAPACITOR
CELL SIZE
DRAM PROCESS
SUP XMLNS

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