Sub-300-ps CBL circuits
- 1 November 1989
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 10 (11) , 484-486
- https://doi.org/10.1109/55.43111
Abstract
Advanced charge-buffered-logic (CBL) circuits featuring double-poly self-alignment, a 'free' epi-base lateral p-n-p (cutoff frequency=300 MHz only), and deep trench isolation are discussed. Using 1.2- mu m design rules and a modified push-pull output stage, a gate delay (fan-in=3) of 278 ps was obtained at a DC current of 30 mu A/gate. The low power-delay product underlies the speed and power potential of CBL as an attractive practical approach to bipolar complementary transistor logic.Keywords
This publication has 3 references indexed in Scilit:
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- Potential of bipolar complementary device/Circuit technologyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1987
- 73ps si bipolar ECL circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1986