Logic Verification System for Very Large Computers Using LSI's

1 January 1979

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 367-374
https://doi.org/10.1109/dac.1979.1600138

Abstract

To aid design verification of very large computers using many LSI's, software tools including a logic simulator with capability of 750,000 gates have been developed.

Keywords

LARGE SCALE INTEGRATION
LOGIC DESIGN
LOGIC TESTING
CIRCUIT TESTING
CIRCUIT SIMULATION
LOGIC CIRCUITS
PROCESS DESIGN
COMPUTER ERRORS
DELAY
OPTICAL DESIGN

This publication has 2 references indexed in Scilit:

Digital Logic Simulation in a Time-Based, Table-Driven Environment
Computer, 1975
Exclusive simulation of activity in digital networks
Communications of the ACM, 1969