Iterative scheme for 1- and 2- dimensional d.c.-transistor simulation
- 27 December 1969
- journal article
- Published by Institution of Engineering and Technology (IET) in Electronics Letters
- Vol. 5 (26) , 677-678
- https://doi.org/10.1049/el:19690510
Abstract
A numerical iterative scheme is presented for the solution of the 1- and 2-dimensional semiconductor d.c. transport equations. This scheme is applied to an n-p-n transistor structure. Input data are geometry, doping profile, boundary conditions and, optionally, mobility dependencies and generation-recombination law.Keywords
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