Specification and verification of system-level hardware designs using time diagrams
- 30 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 9 references indexed in Scilit:
- Bus protocol conversion: From timing diagrams to state machinesPublished by Springer Nature ,2005
- A stimulus/response system based on hierarchical timing diagramsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- OPERATION/EVENT GRAPHS: A Design Representation for Timing BehaviorPublished by Elsevier ,1991
- Verifying the correctness of AADL modules using model checkingPublished by Springer Nature ,1990
- The anchored version of the temporal frameworkPublished by Springer Nature ,1989
- Temporal Logic of ProgramsPublished by Springer Nature ,1987
- “Sometimes” and “not never” revisitedJournal of the ACM, 1986
- Applications of temporal logic to the specification and verification of reactive systems: A survey of current trendsLecture Notes in Computer Science, 1986
- Infinite sequences and finite machinesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1963