A nonvolatile memory FET using PLT thin film gate

1 January 1977

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 294-297
https://doi.org/10.1109/iedm.1977.189235

Abstract

The approach taken in this paper is to develop a low threshold nonvolatile memory switch using the step-like change of the interface built-in potential and its clamping effect in the ferroelectric-semiconductor heterostructure junction with a FET structure A typical performance of the PLT gate GaAs device with a p-channel mode operation is that the writing ("0" to "1" threshold) gate voltage Von=1.5V, the erasing ("1" to "0") gate voltage Voff=6.0V, and the on state drain current Ion=0.1 mA. This operation power level obtained here is about one order of magnitude smaller than that of similar type devices using other ferroelectrics such as Bi4Ti3O12, PZBFN and SbSI. A series of technical data for the fabrication technologies including thin film deposition of the ferroelectric are presented, and the analyses on the device performance are also discussed.

Keywords

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