A methodology and design environment for DSP ASIC fixed point refinement

20 January 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 271-276
https://doi.org/10.1109/date.1999.761133

Abstract

Complex signal processing algorithms are specified in floating point precision. When their hardware implementation requires fixed point precision, type refinement is needed. The paper presents a methodology and design environment for this quantization process. The method uses independent strategies for fixing MSB and LSB weights of fixed point signals. It enables short design cycles by combining the strengths of both analytical and simulation based methods.

Keywords

This publication has 2 references indexed in Scilit:

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