Bipolar dynamic memory cell
- 1 October 1971
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 6 (5) , 297-300
- https://doi.org/10.1109/jssc.1971.1050190
Abstract
A bipolar dynamic memory cell for use in a high-speed random- access memory consists of a cross-coupled pair of transistors and two diodes. Information is dynamically stored using a bistable charge distribution and must be refreshed at a frequency of 1 kHz by a SELECT operation. Standby power per memory cell is in the nanowatt range. The cell requires only 3 interconnect lines and can be fabricated with standard bipolar technology on 12-mil/SUP 2/ silicon area. Cycle time is limited by the speed of decoding, driving, and sensing circuits and is estimated to be 50 ns for a 512-bit RAM chip with complete on-chip decoding.Keywords
This publication has 6 references indexed in Scilit:
- High-speed low-power strobed comparatorIEEE Journal of Solid-State Circuits, 1970
- Design considerations for a high-speed bipolar READ-ONLY memoryIEEE Journal of Solid-State Circuits, 1970
- Memory using diode-coupled bipolar transistor cellsIEEE Journal of Solid-State Circuits, 1970
- Three-transistor-cell 1024-bit 500-ns MOS RAMIEEE Journal of Solid-State Circuits, 1970
- Low-power bipolar transistor memory cellsIEEE Journal of Solid-State Circuits, 1969
- A Study of the Charge Control Parameters of TransistorsProceedings of the IRE, 1960