Physics at the limits of VLSI scaling

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Abstract
The integrated circuit technology is progressing at an unprecedented pace, with a doubling in number of devices per chip every two years. Dimensions are continually being reduced, and no limit is imminent in lithography. Lines narrower than 10nm have been produced. Among semiconductor devices, the MOSFET is predicted to be scalable down to about 100nm channel length—indeed, 150nm channel length MOSFETs have been demonstrated. The bipolar transistor should be scalable to dimensions of the same order. This paper will discuss an attempt to push the limit even further than those projections and in doing so will focus on device physics problems associated with very small devices. Silicon MOSFETs and gallium arsenide heterojunction FETs will be discussed.

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