Abstract
A range of potential architectures that may serve as a basis for the efficient implementation of scheduling algorithms with dynamic order is presented, and the feasibility of these architectures is considered, typically through comparison with common components of communications and computer systems. In the process, possible architectures for implementing static-order algorithms, such as earliest deadline first (EDF), are proposed. Since, to facilitate implementation, some architectures involve a simplification of the desired scheduling algorithm, the resulting performance degradation is explored, and the performances achieved with different architectures are compared. Sorted architectures are discussed, followed by unsorted architectures Author(s) Peha, J.M. Dept. of Electr. Eng., Stanford Univ., CA, USA Tobagi, F.A.

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