Static synchronization beyond VLIW

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Abstract
A key advantage of SIMD (Single Instruction stream, Multiple Data stream) architectures is that synchronization is effected statically at compile-time, hence the execution-time cost of synchronization between “processes” is essentially zero. VLIW (Very Long Instruction Word) machines are successful in large part because they preserve this property while providing more flexibility in terms of what kinds of operations can be parallelized. In this paper, we propose a new kind of architecture — the “static barrier MIMD” or SBM — which can be viewed as a further generalization of the parallel execution abilities of static synchronization machines.Barrier MIMDs are asynchronous Multiple Instruction stream Multiple Data stream architectures capable of parallel execution of loops, subprogram calls, and variable-execution-time instructions. However, instead of using barriers as a synchronization mechanism, the proposed barrier hardware is used to impose static timing constraints. Since the compiler can know at compile time all instructions which each processor could be executing when a particular conceptual synchronization operation is needed, it can resolve most synchronizations by using VLIW-like compile-time instruction scheduling — without use of a runtime synchronization mechanism. The effect is that the proposed barrier mechanism greatly extends the generality of efficient static scheduling without adding a significant hardware cost. Traditional, directed-synchronization, MIMD architectures are more flexible than barrier MIMDs, but the benefits of static scheduling make barrier MIMDs superior for fine to medium grain parallelism. Both the barrier architecture and the supporting compiler technology are discussed in this paper.

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