A 40 MHz 64-bit floating-point co-processor
- 13 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
An arithmetic coprocessor capable of executing 64-bit double-precision floating-point, 32-bit single-precision floating-point, and 32-bit integer instructions has been integrated onto a 1.0-cm*1.1-cm chip in a 1.2- mu m, single-poly, double-metal bulk CMOS process. The chip contains 17000 transistors and includes a register file, two accumulators, and separate interface, multiplication, and addition subprocessors. The coprocessor which is the arithmetic unit for a multichip microprocessor system, is packaged in a 132-pin leadless ceramic chip carrier. The coprocessor can be issued a new instruction each 25-ns clock cycle, and 64-bit double-precision arithmetic with full IEEE rounding is executed at a peak rate of 26.7 MFLOPs (million floating-point operations per second). The waveforms of a store instruction operating at 40 MHz are shown.<>Keywords
This publication has 1 reference indexed in Scilit:
- A 40mhz 32b Cmos Microprocessor With Instruction CachePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1988