Reducing the number of clock variables of timed automata
- 23 December 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 9 references indexed in Scilit:
- Hardware timing verification using KRONOSPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- HYTECH: the next generationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Two examples of verification of multirate timed automata with KronosPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Compositional and symbolic model-checking of real-time systemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A theory of timed automataPublished by Elsevier ,2002
- Symbolic Model Checking for Real-Time SystemsInformation and Computation, 1994
- Model-Checking in Dense Real-TimeInformation and Computation, 1993
- From ATP to timed graphs and hybrid systemsActa Informatica, 1993
- Compiling real-time specifications into extended automataIEEE Transactions on Software Engineering, 1992