Internal architecture of Alpha 21164 microprocessor
- 19 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 10636390,p. 79-87
- https://doi.org/10.1109/cmpcon.1995.512368
Abstract
The internal architecture of a 1200 MIPS/600 MFLOPS (peak) high-performance CMOS ALPHA microprocessor chip is described. This second-generation implementation is the world's fastest microprocessor. It contains a quad-issue superscalar instruction unit, two 64-bit integer execution pipelines, and two 64-bit floating point execution pipelines. The memory unit and bus interface unit combine to form a high-perfomance memory sub-system with MP coherent writeback caches.Keywords
This publication has 2 references indexed in Scilit:
- Testability strategy of the Alpha AXP 21164 microprocessorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 300 MHz 64 b quad-issue CMOS RISC microprocessorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002