A high-speed HEMT 1.5K gate array

1 June 1987

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices

Vol. 34 (6) , 1253-1258
https://doi.org/10.1109/t-ed.1987.23078

Abstract

A 1.5K-gate HEMT gate array has been developed, using a direct-coupled FET logic (DCFL) circuit. The chip, containing 1520 basic cells and 72 I/O cells, was 5.5 mm × 5.6 mm. The basic circuit was designed for two different threshold voltages for D-HEMT, in order to obtain high-speed performance both at room temperature and low temperature. Fully functional 8 × 8 bit parallel multipliers were fabricated on the gate-array chip. At room temperature a multiplication time of 3.7 ns including I/O buffer delay was achieved with power dissipation of 6.0 W at a supply voltage of 1.6 V, and at liquid-nitrogen temperature multiplication time was 3.1 ns where the supply voltage was 0.95 V and the power dissipation was 3.2 W.

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