High-frequency limitations of abrupt-junction FET's
- 1 September 1973
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 20 (9) , 779-792
- https://doi.org/10.1109/t-ed.1973.17746
Abstract
This paper represents analytical results concerning the high-frequency limitations of FET's of junction-gate or Schottky-gate constructions. The intrinsicyparameters are calculated in closed form using the analog RC transmission line method. The bias dependence of various characteristic factors in the y parameters expressions are presented graphically. Equivalent networks including both the intrinsic and extrinsic resistance-capacitance elements are presented and used to calculate the power-gain and frequency limitations of FET's.Keywords
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