Electrical performance and physics of isolation region structures for VLSI

Abstract
A two-dimensional effect in isolation structures is described. It is shown with computer simulations, mathematical analysis, and experimental measurements that the use of trench-like isolation structures significantly improves device electrical isolation, provided junction depths are less than the trench depth. A potential barrier exists at the corners of the isolation region that dominates the parasitic device's I - V characteristics. A mathematical relation for the subthreshold slope as a function of the interface radius is derived which predicts the slope is flatter and the threshold voltage is increased compared to conventional LOCOS structures. This significantly improves the isolation. The position of the potential barrier is shown to allow scaling of the isolation region width without degrading the isolation. Experimental results have verified the predictions of extensive computer simulations.

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