Automatic extraction of higher order interconnect parasitics for device level simulators for VHSIC applications

Publisher Website

24 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/amicd.1996.569380

Abstract

No abstract available

Keywords

This publication has 2 references indexed in Scilit:

Multilevel metal capacitance models for CAD design synthesis systems
IEEE Electron Device Letters, 1992
Simple formulas for two- and three-dimensional capacitances
IEEE Transactions on Electron Devices, 1983