A VLSI chip set for a massively parallel architecture

1 January 1987

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. XXX, 198-199
https://doi.org/10.1109/isscc.1987.1157087

Abstract

This paper will described two chips fabricated in 2μms CMOS. One chip contains 32 processors, and performs 320 million 4bit operations/s. The other chip a communications router, is capable of a throughput of 160Mbytes/s.

Keywords

VERY LARGE SCALE INTEGRATION
PARALLEL ARCHITECTURES
CIRCUIT TESTING
DELAY
THROUGHPUT
SWITCHING CIRCUITS
PROTOCOLS
REGISTERS
WIRES
FABRICATION

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