Static and transient latchup simulation of VLSI-CMOS with an improved physical design model

1 June 1987

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices

Vol. 34 (6) , 1290-1296
https://doi.org/10.1109/t-ed.1987.23083

Abstract

We are presenting an improved latchup design model for static and transient latchup simulation of VLSI CMOS devices. The model is based on a decomposition of the CMOS structure into a network of analytically described current elements for both majority and minority carriers. Average doping densities and geometrical parameters are the physically based input data. For the modeling of the 2-D majority-carrier flow, transmission-line elements are introduced, especially in the inhomogeneously doped transition region between the substrate and an epitaxial layer. For modeling the transient current behavior, diffusion and space-charge capacitances are used. The model yields very good agreement with measurements both for static and transient triggering modes. Due to the physically reasonable assumptions used in the model equations, the influence of design variations on latchup characteristics can be predicted adequately without new parameter fitting.

Keywords

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