Strained Si NMOSFETs for high performance CMOS technology
- 13 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Performance enhancements in strained Si NMOSFETs were demonstrated at L/sub eff/<70 nm. A 70% increase in electron mobility was observed at vertical fields as high as 1.5 MV/cm for the first time, suggesting a new mobility enhancement mechanism in addition to reduced phonon scattering. Current drive increase by /spl ges/35% was observed at L/sub eff/<70 nm. These results indicate that strain can be used to improve CMOS device performance at sub-100 nm technology nodes.Keywords
This publication has 3 references indexed in Scilit:
- Fabrication and analysis of deep submicron strained-Si n-MOSFET'sIEEE Transactions on Electron Devices, 2000
- Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloysJournal of Applied Physics, 1996
- Comparative study of phonon-limited mobility of two-dimensional electrons in strained and unstrained Si metal–oxide–semiconductor field-effect transistorsJournal of Applied Physics, 1996