A fully parallel VLSI implementation of distributed arithmetic

6 January 2003

proceedings article
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/iscas.1988.15217

Abstract

A novel architecture to implement distributed arithmetic in VLSI is presented. This architecture comprises a serial-in random-out multiport memory and a multi-input adder. The design of a 1.25- mu m CMOS convolution processor chip based on the architecture is reported. Issues in the development of chip architecture and design tools are discussed.

Keywords

VERY LARGE SCALE INTEGRATION
ARITHMETIC
READ ONLY MEMORY
COMPUTER ARCHITECTURE
DISTRIBUTED COMPUTING
SHIFT REGISTERS
CLOCKS
HARDWARE
CMOS PROCESS
ZINC

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