Analysis of high electron mobility transistors based on a two-dimensional numerical model

1 December 1984

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters

Vol. 5 (12) , 508-510
https://doi.org/10.1109/EDL.1984.26007

Abstract

A two-dimensional numerical model is employed to simulate the device performance of the high electron mobility transistor. A 1- µm gate device is analyzed using the equilibrium velocity-field characteristic of GaAs. The calculation reveals existence of electron accumulation in the GaAs layer under the drain side end of the gate electrode. A quasi-piecewise linear velocity-field characteristic is also employed to simulate the velocity overshoot effect. The cutoff frequency is found to be improved by about 50 percent owing to the velocity overshoot effect.

Keywords

HEMTS
MODFETS
NUMERICAL MODELS
GALLIUM ARSENIDE
ELECTRON MOBILITY
HETEROJUNCTIONS
ERROR ANALYSIS
POISSON EQUATIONS
PERFORMANCE ANALYSIS
ELECTRODES

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